1. Field of the Invention
The present invention relates to a data transmission between devices such as semiconductor chips, having a high-speed interface.
2. Description of Related Art
As seen in a data transmission between a processor LSI (Large Scale Integration) and a chipset LSI in a computer, when a data transmission is performed between semiconductor chips, it is essential to provide a sufficient setup and hold times for a data signal. According to the conventional method, as disclosed in JP-A-8-102729 for instance, a clock signal of a transmitter chip is transmitted to a receiver chip, which delays the received clock signal to ensure the setup time and hold time.
FIG. 1A shows a structure for transmitting parallel data of plural bits according to the conventional source synchronous method. The transmitter chip 11 has a delay circuit 21, flip-flop (FF) circuits 22-i, and output circuits 23 and 24-i (i=1, 2, . . . , N), while a receiver chip 12 has input circuits 25 and 26-i, and flip-flop circuits 27-i (i=1, 2, N).
The source synchronous method is such that when a data transmission is performed between such chips, the clock signal used in the transmitter chip 11 (or the receiver chip 12) is given a fixed delay and transmitted together with data signals to the receiver chip 12. In the receiver chip 12, the data signals are strobed with the clock signal transmitted from the transmitter chip 11, as shown in FIG. 1B.
The fixed delay given to the clock signal is determined, by taking into consideration various delays (e.g., of board wiring, internal wiring of LSI, and driver/receiver) and process variation, to be within a range ensuring the setup and hold times of the flip-flop circuits 27-i in the receiver. The wiring between the chips is, in principle, an equal length wiring, for reducing a phase variation between/among channels of a transmission path.[0006]
The source synchronous method is advantageous in that it is relatively easy to create an adjusting circuit, since adjustment is required merely for the clock signal. However, it is required that a range of phase variation between/among data signals strobed by the single clock signal be narrower than one cycle of a frequency of the transmitted clock signal. Thus, the source synchronous method has the following limitations:
(1) The wiring between the chips should be an equal length wiring.
(2) The number N of data bits strobed by the single clock signal should be relatively small.
(3) Even if the conditions (1) and (2) are satisfied, data transmission may be impossible in view of a phase variation depending upon the process and transmission degradation.
Each of the following documents relates to a parallel/serial data transmission, a clock signal adjustment, a skew adjustment, a clock signal generation, a timing control, or the like: JP-A-8-102729, JP-A-2000-285144, JP-A-8-044667, JP-A-10-164037, JP-A-2002-044061, JP-A-6-177940, JP-A-8-054955, JP-A-2002-108642, JP-A-2000-134189, JP-A-11-163846, JP-A-5-336091, JP-A-2000-341135, JP-A-2002-223208, JP-A-2003-273852, JP-A-5-225079, and JP-A-5-336210.
In the above-described method where the transmitter chip transmits in parallel the clock signal and a parallel data signal, the range of phase variation with respect to the same clock signal between/among data signals each consisting of a single bit is limited to within one cycle of the frequency of the clock signal. Therefore, it is difficult to realize a high transmission rate. Further, due to the demand of reducing the phase variation between/among data signals each consisting of a single bit of data (which may be hereinafter referred to as a “one-bit data signal”), the constraints including the necessity of wiring the chips to each other with an equal length wiring increase, making designing the package wiring more difficult.
In another method where a function for transmitting a clock signal is not included, but only a function for adjusting a phase of a local clock generated in a PLL (phase-locked loop) in the receiver chip is provided, the requisite that the setup and hold times be ensured may not be satisfied due to a long term jitter in the PLL of the receiver chip.
FIG. 1C shows an ideal clock signal without jitter, as well as a clock signal with a long term jitter as an extreme example. FIG. 1D shows a variation in a clock frequency with time. For instance, when the frequency of the clock signal of a PLL of the transmitter chip becomes high while the frequency of the clock signal of the PLL of the receiver chip becomes low, the requisite of ensuring the setup and hold times may not be satisfied even if each local clock is adjusted.